Hello. We are planning to use either the SLG46824 or SLG46826 device in some new products and really welcome the multi-time programming over I2C of these components - simply due to lower risk vs. use of OTP.

We have built up the IP over this last weekend and the simulation is showing promise to be correct. Will test against the true hardware this week on your kits.

A few questions on this component and sourcing:

1) The pricing appears to be the same for 100 pcs of either component. Are these supplied on cut tape? How can we purchase on T&R with the necessary leader tape for automated SMT mounting of the PCBA? After our validation, we are fine to purchase on full T&R qty. Is that the only way to receive with the leader tape and in full T&R qty?

2) What is the difference between the SLG46824 vs. SLG46826 with respect to the internal 2k EEprom? It appears both devices have an internal 2k EEprom but the BLOCK diagram inside the SLG46824 datasheet does not offer the "2K EEprom Emulation" block in the graphic. Is that a documentation error?

3) Any plans to offer the same features of I2C programming AND have internal ASM support? Would be nice to have which appear to be missing from these 2 devices.

Finally, in building our 3 stage reset sequencer IP and using the simulator with DLY0 and/or DLY1 - the simulator would not show us any changes to our expected delays. That is, the rise of the DLYx output followed the VDD rail when we expected some programmed delay for this rise. Not sure if this was our fault as after investing a few hours and introducing other DLYx blocks, the simulation worked fine. Not logical but that was our experience. In the end, we do not believe we did anything different but the simulation started to work (using the PROBES to monitor). Will see if we can replicate the quirk but for now, since we appear to be operational, it is not a worry.

For closure, will test on the hardware kits.

Thanks!