首先,我们为SPI_CLK (Port/Pin p0_ 0)配置了GPIO,像几个演示代码和HCI演示那样输入:被干扰的接收/发送字节和被干扰的MISO行使用(不是CLK对齐的MISO过渡)。当我们把SPI_CLK引脚改为OUTPUT (for Slave !?)时,它工作得很好:
- GPIO_ConfigurePin(SPI_CLK_GPIO_PORT, SPI_CLK_GPIO_PIN, OUTPUT, PID_SPI_CLK, false);
2) SPI Slave should ignore Master CS (SPI_EN)?
We enabled the DA14580 SPI Slave CS usage as described in demo code and HCI demo, to use the master driven CS:
- SetBits16(SPI_CTRL_REG,SPI_EN_CTRL,1);
But together with the conditions above, it does not work: It leads into the same disturbed IRQs/Rx/Tx bytes as described above. Switching CS-usage off makes all signals reliable:
- SetBits16(SPI_CTRL_REG,SPI_EN_CTRL,0);
Pls. note, that the SPI Master (STM32) generates well terminated SPI signals, decoded by a LogicAnalyser without errors. Master CS (of course low-active) goes to LOW ~7 us before CLK starts with first transitio, and goes back to HIGH ~7us after the last CLK transition (all 125 kHz SPI-CLK frequency).
So our question is: Is SPI_CLK and SPI_EN usage as described above intended for a DA14580 SPI Slave?