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Simulation problem with F(1) macrocell on SLG46880V

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I'm using the F(1) computational macrocell on a SLG46880V device. It looks like when computations are performed using the cell on inputs coming from the dedicated analog comparator pins, and the outputs of the F(1) block are routed to the FSM transition inputs, the states don't transition correctly in the simulation.

当路由输入从马一般的连接trix it seems to work OK. Please see links to images and exaple file:

https://imgur.com/a/liAV0ZG

Possible Bug in the Comparitor Hysteresis View

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GreenPAK and GreenFET questions

Hi guys,

We implemented a comparitor hysteresis in GreenPAK3 Designer v6.12 and weren't seeing the results we expected. It appears that the software is giving misleading guidance on what to expect. When looking a the description for the comparitor it says:

200mV: is a +0mV and -200mV hysteresis. For Vref=1V, the trigger points will be 1V and 0.8V. Only applies if Vref is internal;

However the software shows with an IN- Source of 1000mV typical ACMP thresholds of:

V_IH (mV) 1100 and V_IL (mv) 900

Bug in arch_main.c

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Dialog Smartbond Bluetooth Low Energy – Software

There is a bug in arch_main.c

The cs_table is currently declared as an uint8_t array and therefore has alignment 1. However, during the booting there are store instructions that stores 16-bit data into this buffer.
I happen to have variables in my app that makes the cs_table getting an odd address when I look at the .map file. Then the hardfault handler gets executed during the booting.

After I change __attribute__((section("cs_area"), zero_init)) to __attribute__((section("cs_area"), zero_init, aligned(2))), it works good again.