I am interested in using the DA9062 PMIC for a Zynq 7010 product. The data sheet has recommendations for capacitors, but I did not see much information about the requirements for them, such as min/max capacitance, package size, quantity, ESR, ESL, etc. The datasheet says"When selecting a capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be taken into account". I understand what DC bias is, so this suggests it is possible to use alternate components than those recommended. But I would like to understand what the limitations are.
是否选择了推荐的组件来说明PCB布局的小程度如何？或者他们选择，因为小包装尺寸将具有较低的安装电感？是并行使用的多个组件，以进一步减少ESR和ESL？或者是多个较小的值，用于在减少生产中使用的电容器数量时提供灵活性？是否有可以使用的最大电容量？
Xilinx recommends certain values for the Zynq 7010, such as 100uF for bulk capacitance. If possible I would like to use the same capacitors for the PMIC regulators. I have 100uF 1206 capacitors, which I hope will work well because capacitors are very hard to procure these days!
谢谢，
电动器
Hello ElectronHerder,
Let me talk with the team and get back to you.
Kind regards,
Elliott Dexter
Hello ElectronHerder,
We state in the DA9062 datasheet the tolerances for Capacitor's, ESR and Inductors (I have attached an example image), they can be found in the electrical characteristics part of the datasheet. Some of these parameters are not listed in the "component selection" section; this section is for specific recommended components. The components we recommend have been chosen for a small PCB sizem whilst maintining performance.
Kind regards,
Elliott Dexter
谢谢艾略特指向that out. I'm sorry I didn't see it. In the past I have used a lot of Texas Instruments parts, and their data sheets usually have a section on component selection that includes formulas and a description of the limitations. I guess I'm a creature of habit, and didn't think to look in the in the Electrical Characteristics section.
是基于满载的输出电容要求吗？例如，如果降压1以全电流模式运行但仅驱动1.25A最大值，则所需的电容会少？我不是要求特定的数字，只是一个泛化。稳定性与最小纹波规格需要多少电容？
Why is there a max spec for the output capacitor? What happens when you have too much capacitance? Does it become unstable? The regulator will be supplying current to a circuit that includes a significant amount of decoupling capacitance, so I am assuming that this must only be referring to the capacitors that are physically very close to the inductor.
Here is a link to the data sheet for the 100uF capacitor that I am using:
http://www.samsungsem.com/kr/support/product-search/mlcc/__icsFiles/afie...
我不确定如何应用ESR图the DA9062 ESR spec. The spec says "f > 100 kHz", which I take to mean all frequencies above 100 kHz. Is that right? I'd say this capacitor is pretty close to meeting the spec at 100 MHz. I believe your reference design uses two capacitors in parallel to halve the ESR and impedance. If I use this capacitor do you see any issues? How much benefit is there in using two capacitors in parallel?
谢谢，最好的问候，
电动器
Hello ElectronHerder,
The recommend output capacitance is based upon full load. That’s why we have listed two different sets of recommended capacitors and their tolerances. Please see attached diagram for an example.
The main effect of increasing the output capacitance of the buck converter beyond the recommended maximum capacitance value would be an increase in buck start-up time and effect the slew rate. I cannot see why using 1 x 100 uF over 2 x 47 uF would greatly affect the start-up time. We chose to use two capacitors in parallel instead of one capacitor to reduce ESR, if the capacitor you plan on using is similar to our spec ESR then it should be ok.
The capacitor looks to be ok, however the link you sent me doesnt have the ESR over temperture.
Kind regards,
Elliott Dexter
谢谢艾略特。我不确定你的回答是否完全解决了我的问题。两组电容值对于设备的两种不同的操作模式。在半流程模式下，禁用了一半的通电设备，这意味着输出阻抗与全电流模式不同。我很奇怪电容器要求是用于全电流模式的东西，但在最大负载势电流的一半。有时我会提出不切实际的问题，以帮助我了解事情的工作。
Your answer about the main effect of increasing the output capacitance was enlightening. It appears the sequencing of the PMIC is based on time, not whether a voltage of one supply has been reached before starting the next supply. Kind of "open loop" instead of "closed loop". Is that a fair way to describe it?
Thank you for looking at the data sheet for the capacitor. I will see if I can find more data on ESR over temperature.
Kind regards,
电动器