What are the data to clock setup and hold times for DFFs, Pipes, PGens and counters for the SLG46620 device, at the 3 VDDs? These are not listed in the device's datasheet (ver 113).
一个lso, how do you define specs like "CNT/DLY opposite to selected edge delay", and "CNT/DLY (Shared) opposite to selected Edge Delay" for the counters?
Thanks,
...Craig
Device:
Device Number:
SLG46620
Hi Craig,
Thanks for your question. Unfortunately we don't have setup and hold time listed in the datasheets yet. Hope we will update that data soon.
Selected edge delay is the edge which was choosen to be delayed by CNT/DLY block e.g. "rising". Therefore "falling" is opposite to selected edge and it shouldn't be delayed but there is some propagation delay of macrocell (see attached). This parameter was called "CNT/DLY opposite to selected edge delay". Some macrocells can be configured as different blocks e.g. LUT/DFF/DLY so they have shared functions. Those blocks have note "(Shared)" in the describtion and may have different parameters than non-shared blocks.
Hi Pavlo, I realize that info is not in your data sheets, which is why I asked. Could it can be provided in the form of a simple spreadsheet rather than making the datasheet even longer?
The absence of that data has not prevented me from using the SLG46620 as my designs use conservative timing. But it is easy to see that these parts may get ruled out of tighter-tolerance designs simply because you cannot tell whether it should work, while another MFG's parts spec may contain the information required to confirm their operation.
Regarding the "selected edge delay", I don't follow your explanation. Is that parameter equivalent to "Clk to Count_End delay" for the counters?