My requirement is on input side pulses will be coming. When ever there is high or low on input side for a certain amount of time a pulse should be generated on output side.
Reset is driven to low when the Input stop high-low toggling.
Basically you can relate that to a watchdog timer implementation.
I am attaching a design in which i am not getting the desired output.
I am also attaching my requirement picture.
Kindly help me.
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SLG46621
Hello Lenin,
I have been taking a look at your design and I believe I have a couple of solutions that may suit your application. It looks like your requirement is the following:
1. There are several watchdog inputs, each with their independent output.
2. If any do not receive a pulse for 1s a LO will occur on their respective RESET line at the rising edge of the next clock.
3. At the next rising edge of the clock the LO signal will return to HI.
It looks like there are several IO, such as EN1.8AB, that are not yet connected and may require GreenPAK components, so I've tried to formulate a solution that only uses the same number of components that you've used previously per channel. The attached .zip file shows an example of a solution that may work for you; after 1 second of RXD1 remaining either HI or LO the DLY block will fall LO. This will trigger a LO signal across ResetA at the rising edge of the clock, and will continue until the next rising clock edge. HOWEVER, this pulse will occur every 1s that the watchdog doesn't receive a signal. In order to create a one-shot pulse more components would be required. Let me know if this solution is acceptable or if you need assistance drafting a more compatible solution with your design.
I apologize, the previous zip file didn't have the updated example design.