Hello everyone,
questions:
1. From which (VDD or VDD2) is the power supply to the internal blocks (such as counters, comparators, oscillators, etc.) SLG46824/826?
2. Can we say that VDD is primary and main, and VDD2 is auxiliary?
3. Can I work without connecting VDD2 at all?
4.有“电源域”?
5. If so, which internal blocks are connected to which domain?
6. What is the best way to connect LEDs (pulses of tens of milliamperes with a frequency of several kHz), so that the current pulses do not affect the accuracy of the comparators (and other blocks)?
7. Where can I find PSRR(power supply rejection ratio)-VDD and PSRR-VDD2 for Vref, comparator thresholds and oscillator frequencies?
Thanks!
Device:
嗨,小姐khail,
1. All blocks in SLG46824/826 devices are connected to VDD. The VDD2 is dedicated only to its IO pins(yellow in the Designer).
2. Yes.
3. Yes, but without access to VDD2 IO pins.
4.NO
5.-
6. One of the available cases is to flash the LED by an output HIGH sourced from VDD2 and use ground "star". Also, split VDD and VDD2 using different LDOs.
It depends on your specific application.
7. The oscillator frequencies you can find in base datasheet as well as ACMP's hysteresis drift. Typical comparator thresholds are given at the GPAK Designer. I don't have any info about PSRR and not sure we can provide it.
Thanks and regards,
Pavlo