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thelger
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Boot from SPI Master

Hi,

I've just spent several hours with trying to find out, what is wrong with my hard and software!
Here is my experience, which might be helpful for anybody, who is going to design a system that boots a DA1458x from a master MCU via SPI:
Our device contains a STM32Fxxx MCU, and an ALPS UGMZ2AA module (AFAIK DA14580 inside) and SPI flash memory, both sharing the same SPI peripheral of the main MCU. The flash memory, as well as the UGMZ shall be both accessable as SPI slaves during normal operation, therefore it's not possible to connect the UGMZ as master to the flash menory.
I have written some code for loading the image data from the flash memory into the MCU and then transfering them to the Bluetooth module, according to boot protocol from document "AN-B-001 - Booting from serial interfaces v2.0". While debugging the program, I was happy to see the UGMZ responding with ACK (0x02) for the preamble and image length data.
But the SPI data look like this:

Byte MOSI MISO
# (P0_5) (P0_6)
0 0x70 0x00 (Preamble)
1 0x50 0xDC
2 0x00 0xD4
3 0x00 0x02 (MOSI: Prg.size LSB, MISO: ACK, as expected)
4 0x1A 0xC0 (MOSI: Prg.size MSB)
5 0xD1 0xC6 (MOSI: CRC)
6 0x00 0x02 (MOSI: Mode Byte = 8-bit mode, MISO: ACK for length, as expected)
7 0x00 0xC0 (MOSI: empty)
8 0 x00 0 xff(莫西人:第一个数据字节,味噌:Problem -> ACK expected!)

Problem is byte #8, which should be ACK, according to AN-B-001

So I tried to find out what could be wrong here, also searched this forum and found several other posts about that issue, e.g.https://support.dialog-semiconductor.com/forums/post/dialog-smartbond-bl...
既然话题总是对话框的答案was about likely SPI transfer problems and that the DA1458x's SPI in slave mode might be somewhat critical ("The spi sampler when in slave mode its very sensitive to spikes and reflections"), and since AN-B-001 is meanwhile quite old, without further updates released, I didn't assume that the documentation could be wrong. So I assumed the problem is related to my hard- or software. But even with a second test hardwarre, completely different from our device production sample (another MCU board, connected to ALPS development board, tried SPI connection for both variants according to Step 1 and Step 2, the result was always the same and I had no idea what's wrong.
On our device, SPI trace length between MCU and slaves is just a few millimeters, so I could not really imagine a problem of reflections there, nor could I see anything suspicious on the oscilloscope.
In desperation, I've tried to transmit just a little "test-image" of 4 bytes, by simply ignoring the missing ACK at byte #8 :

Byte MOSI MISO
0 0x70 0x00 (Preamble)
1 0x50 0xDC
2 0x00 0xD4
3 0x01 0x02 (MOSI: Prg.size LSB, one 32-bit word = 4 bytes, MISO: ACK, as expected)
4 0x00 0xC0 (MOSI: Prg.size MSB)
5 0xFF 0xFF (MOSI: CRC)
6 0x00 0x02 (MOSI: Mode Byte = 8-bit mode, MISO: ACK for length, as expected)
7 0x00 0xC0 (MOSI: empty)
8 0 x00 0 xff(莫西人:第一个数据字节,味噌:ACK expected, FF = garbage, ignored)
9 0x00 0xFF (MOSI: data byte)
10 0x00 0xFF (MOSI: data byte)
11 0x00 0xFF (MOSI: last data byte)
12 0x00 0xAA (MOSI: empty, MISO: :) )
13 0x00 0x02 (MOSI: empty, MISO: :) wow! Surprise - obviously that worked!)

My Conclusion: Seems that DA14580's bootloader does not fully comply to the document AN-B-001.
Question: did anybody ever see an ACK from the bootloader at byte #8?
@Dialog: if I'm right and the doc (AN-B-001) is wrong, please release a corrected version! It is rather frustrating to spend hours and hours to search for bugs that do not exist, due to misleading documentation!

Further I found out:
I never saw any "NACK" (0x20) - if you send garbage, e.g. if the given length of the image is beyond the DA1458x's memory size, you'll get garbage back (= anything, but "ACK), so do not really expect "NACK" (0x20) for errors.
Nice:
It seems to be allowed to deselect the SPI slave (CS high) between any two data bytes and resume SPI transmission later by setting CS low again. This is very helpful for our application, because the flash and the Bluetooth module share the same SPI pins on the MCU. So I guess I can fetch the image in small packets from flash and send them to the module, rather than having to load and transmit the whole image as a single, large block. I did not find anything about that in the documents, so I tried out by setting CS high after each byte, which seems to work. But I did not yet finally test it with real image data though....

Device:
MT_dialog
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加入:2015-06-08 11:34
Hi thelger,

Hi thelger,

Regarding the sensitivity of the 580's SPI module, due to spikes and reflections, is a valid issue, and in most of the cases, this was the reason that there wasn't any communication from the 580's side towards the master.

Regarding you issue, indeed the document has an inaccurancy at that point, the ACK byte at step 8 isn't exactly at step 8 but at the end of the download sequence, so if the master starts downloading he will get a 0xAA (depending on the mode) and a 0x02 or a 0x20 if the device's CRC doesn't match with the CRC that the master send at the image header. I informed the team regarding this misleading note on that specific section.

Thanks for the indication.

最好的问候mt_dialog.

thelger
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Last seen:2 years 8 months ago
加入:2016-10-11 10:58
Hi,

Hi,

here is a little update: Meanwhile I managed to send complete image data to the Bluetooth module, but the process seemed to be not very reliable. Quite often, the data were corrupted and instead of ACK, I got some garbage back (not NACK!) at the end of transmission. When there is no curruption, the bootloader sends 0xFF during trtansfer of the the whole data section and then 0xAA, 0x02 (ACK). If data are corrupted, reply is 0xFF for the image data, too, but then something like 0x55 0x10. This seems to be 0xAA 0x40 (NAK), right-shifted by one bit, so it looks like the DA14580 SPI slave is missing one SPI clock pulse!
Obviously, the error appears right at the beginning of the transmission (see attached picture). I found, that the data get corrupted when there is that little spike visible on MISO line between bytes #7 and #8, followed by byte (0x7F) for MISO byte #8. In case of a "good" transmission, the spike is not there and MISO byte #8 is 0xFF.
I found that the transmission seems to work reliable if there is a little break of a few microseconds in between bytes #7 and #8, like shown in the bottom part of the picture.

Best regards,

Thomas Elger

Attachment:
MT_dialog
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加入:2015-06-08 11:34
Hi thelger,

Hi thelger,

Thanks for sharing your foundings, i am sure that this will be a great help to anyone who has similar issues with booting from an SPI master. Regarding the 0x55 and the 0x10 that you see its actually a 0xAA and a 0x20 (NACK) shifted one bit and it should be due to the spike that appears on the logic analyser capture (SPI module operating in slave mode, sensitive in spikes and reflections). Since with a few milliseconds break guarantees in your case the reliable transmition of the image, then perhaps lowering the SPI master clock frequncy would be worth trying.

Thanks MT_dialog

thelger
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Last seen:2 years 8 months ago
加入:2016-10-11 10:58
Hi MT_dialog,

Hi MT_dialog,

> Regarding the 0x55 and the 0x10 that you see its actually a 0xAA and a 0x20 (NACK) shifted one bit
uuups - sorry, that's what I meant! My "0x40" was just a typo.
> and it should be due to the spike that appears on the logic analyser capture (SPI module operating in slave mode, sensitive in spikes and reflections).
Well, the spike is on the MISO wire, so it's caused by the DA1458x itself, I don't think that this is the reason for the problem - it looks more like a symptom of the problem. Apart from that, I could not see any difference in the numbers of good vs. bad data transfers, whether there was only a few mm PCB trace., or 20 cm additional wire for connection of the logic analyzer attached to the signals. Even on a scope (500 MHz Tektronics), the SCK and MOSI signals were pretty clean. If really the line quality (reflections etc.) would be that critical, the additional wires and also changing the SPI port's output slew rate by various speed settings should have a clear influence on the number of faults, but I couldn't see that.
> then perhaps lowering the SPI master clock frequncy would be worth trying.
是的,如果它很容易,我会尝试这个,但我们的主要MCU以72 MHz运行,最小SPI时钟频率为CLK / 256 = 0.28 MHz。目前我不想重新配置系统时钟树只是为了测试,而那么短暂的休息更容易实施并解决问题。;)但我想,较低的SPI时钟频率也可能解决它。

Thanks for your attention!

Best reards

Thomas Elger