What are the data to clock setup and hold times for DFFs, Pipes, PGens and counters for the SLG46620 device, at the 3 VDDs? These are not listed in the device's datasheet (ver 113).
Also, how do you define specs like "CNT/DLY opposite to selected edge delay", and "CNT/DLY (Shared) opposite to selected Edge Delay" for the counters?
Thanks,
...Craig
In application with SLG59H1128V, Can I have RSET value in 0.75A for Active Current Limit?
According to datasheet there's no statement for less than 1A of current limitation.
你好,我昨天发布but I don't see my post so I am posting it again
Hi,
Hi,
I am using Da14850 device in my project. I would like to know much about audio in Da14850. Where can I get the information?. Thank you.
Please see details in attached PDF with timing data.
Thanks,
Paul.
When I finish debugging my software, I want to download firmware to the OTP of chip. I plan to download the firmware to the chip by UART, for example, can I use the the pins of P0.4 and P0.5 to connect to my PC? do you have any guidelines about hardware connection and software operation? Thank you!
I'm trying to enable the sidetone feature for the DA7218 audio codec. Both microphone and speaker work fine. However the sidetone doesn't work.
I'm using the DA14195DEVKTD with SDK v.1.6.2.
Hi,
I'm trying to estimate the total delay from an input pin to an output pin when configuring the SLG46539 as a dual-supply level shifter. The inputs will come from the low-voltage 1.8V domain (VDD2) and need to be level-shifted up to 2.7V - 4.2V (VDD). There should be no other logic or gates in this signal path. We can assume the output pin is driving a 10pF load.
Thanks!
My Dip and Advanced boards arrived today.
I have some 108 chips on the 20 pin headers.
I have the dip board connected to the PC, and selected as my debug platform but I have no success trying to debug on the chip.
All options are grey except for change platform, Import configuration, and some of the pin control buttons like Int Vdd, Ext Vdd.
I tried applying 3V between pins 1 and 11, nothing changes.
I'm missing something on getting into debugging, but what?
We would like to use the watchdog timer as a safety mechanism. However, we cannot seem to get it to run. The system_init() fuinction does indeed start it running, but then it is turned off (frozen) in several places, such as the periph_init() function (this operates directly on the registers), and also in main_func() before sleep. But we do not seem to be able to find anywhere where it is resumed (via wdg_resume() I would expect). I presume this should happen on wake, but we can't find it. Yet the documentation implies that it will be running.
