Hi Dialog,
I am using your SPI driver and configure it as slave mode. The Rx side seems to be fine, but for Tx side, I always get two bytes of junk data(always the last two bytes of the previous package).
e.g.
I want to send 01 02 03 04 05 for the first package and data received by master side is 00 00 01 02 03; I send the package again and for this time, data received by master is 04 05 01 02 03.
The source code is pasted below:
void ld_spi_init()
{
//arch_printf("spi init function is called\n");
SPI_Word_Mode_t bit_mode = SPI_MODE_8BIT;
SPI_Role_t role = SPI_ROLE_SLAVE;
SPI_Polarity_Mode_t clk_pol = SPI_CLK_IDLE_POL_LOW;
SPI_PHA_Mode_t pha_mode = SPI_PHA_MODE_1;
SPI_MINT_Mode_t irq = SPI_MINT_ENABLE;
SPI_XTAL_Freq_t freq = SPI_XTAL_DIV_2;
spi_init(&cs_pad,bit_mode,role,clk_pol,pha_mode,irq,freq);
//SetWord16(SPI_CTRL_REG1,(GetWord16(SPI_CTRL_REG1)|0x0003));
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn,0);
NVIC_EnableIRQ(SPI_IRQn);
return;
}
// 4M bitrate/500k bytes looks safe
void SPI_Handler(void)
{
uint16_t a,b;
count++;
b = count;
//arch_printf("b = %04x\t", b);
//SetWord16(SPI_CLEAR_INT_REG,1);
if(spi_flag == 0)
{
c = 0x01;
spi_flag = 1;
SetWord16 (GPIO_IRQ0_IN_SEL_REG, 2);
SetWord16(GPIO_INT_LEVEL_CTRL_REG, 0x0000);
GPIO_RegisterCallback(GPIO0_IRQn,GPIO0_Irq_Handler);
NVIC_ClearPendingIRQ(GPIO0_IRQn);
NVIC_SetPriority(GPIO0_IRQn,1);
NVIC_EnableIRQ(GPIO0_IRQn);
}
else
{
c++;
}
a = spi_access(count);
//arch_printf("rx: %04x\t",a);
return;
}
void GPIO0_Irq_Handler(void)
{
if(spi_flag == 1)
{
spi_flag = 0;
count = 0;
SetWord16 (GPIO_IRQ0_IN_SEL_REG, 0);
NVIC_ClearPendingIRQ(GPIO0_IRQn);
NVIC_DisableIRQ(GPIO0_IRQn);
arch_printf("spi transmit done, c = %d\n",c);
}
SetWord16(GPIO_RESET_IRQ_REG,1);
}
Could you please help me with it ?
谢谢!
Hi zwang308,
I think that the problem is caused by the fact that you are accessing the SPI slave when no data are allready placed in the FIFO this results in reading two zeroes then the other 3 bytes are getting in your FIFO and you are able to read them. You have to make sure that there are data in the FIFO before reading it.
Thanks MT_dialog
Hi MT_Dialog,
According to the specification in DA14580's datasheet page100, Table 149, SPI_CTRL_REG1, default value of SPI_FIFO_MODE is 0x03 and I think that means no FIFO used.
In your driver spi_init function, I don think it change SPI_FIFO_MODE value. So, I think in my application, SPI controller does not use the FIFO.
Could you please help me to verify this information?
Thanks
Hi zwang308,
Yes thats right. In the driver no FIFO is used, and the reset value of the register is 0x03. But since you get shifted data by two bytes i guess that you read the data register when it has no data. Maybe you should check the receiving code of the other MCU. The data that you send from the da and are shifted, do you print them to a terminal from the master's side? also can you check the bus with a logic analyser ? Also what is the SPI clock that your master uses ? since you are using 8MHz SPI clock in the da try to use 2MHz as master clock.
Thanks MT_dialog
Hi MT_Dialog,
I use Total Phase's AARDVARK emulator as SPI master and I use USBee Rx as a logic analyzer to check data on the bus. All my tx data from master is correct and tx data from Da is shifted by two bytes. So, I suspect the problem is on DA's firmware side.
Thanks,
Do we have any update? Thanks
Hi zwang308,
I used two da's as master and as a slave, i managed to get all the data from the slave to master with no shifted bytes. If you clock the slave without putting something in the FIFO, when the spi_access function is called the slave is going to trasmit zeros and then load the value you want into the transmit register so the next value should be the number you 've loaded into the previous ISR call. Have you tried to lower your clock on the master's side and increasing the clock on the da (slave)? Also can you please try to directly access the register SPI_RX_TX_REG0 please clear the spi interrupt flag?
Thanks MT_dialog
Hi MT_dialog,
Thanks a lot for the information. I think I get want I need.
Thank you!