Which pins should be used for the SWD interface to a QFN24 DA14531? The reference board designs all use P0_2 for SWCK and P0_10 for SWDIO. The DA14531 datasheet shows PO_5 as the default pin for SWDIO with P0_10 as an alternate. The alternate is programmed according to the setting of SYS_CTRL_REG[8:7] but these pins default to 0x0 on reset, which is debugger disabled unless the OTP header is programmed otherwise. So when I get a new unprogrammed part from the factory, if the SYS_CTRL_REG defaults to debugger disabled on power up, how do I get the SWD port to connect and which pins will it use?
Device:
Hi There,
You could use same GPIOs as our DKs - P0_2 for SWCK and P0_10 for SWDIO. In order to disable the debugger interface permanently, the "Debugger disable" (0x70000000) filed in the OTP configuration script should be programmed.
In case you want to re-map the SWD interface, you should follow the steps below :
Thanks, PM_Dialog
I am using the same pins as your dev kits. I don't want to disable the debugger, I want to know how to enable it on new parts. According to the datasheet (CF0011-120-00 Rev 3.1, page 197, table 126, row 4) SYS_CTRL_REG[DEBUGGER_ENABLE] is 00 on reset which means the debugger is disabled. Is the datasheet incorrect?
Hi There,
If you run any of the SDK examples in debug mode and read the SYS_CTRL_REG[DEBUGGER_ENABLE], you will see that the value is 0x03. This means that the SWD pins are mapped on P0_2 for SWCK and P0_10 for SWDIO. The datasheet is correctly- if the SYS_CTRL_REG[DEBUGGER_ENABLE] is explicitly programmed with 0x0 then no debugger is available.
Thanks, PM_Dialog