Dear Dialog,
DA14580 has two timers, each has its own register bit to switch it on/off
TIMER0_CTRL_REG[TIM0_CTRL]
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]
Also there is a bit CLK_PER_REG[TMR_ENABLE] that switches clock of both timers.
Is it OK to leave CLK_PER_REG[TMR_ENABLE] always on?
Will it lead to noticeable power consumption or will it prevent chip from entering sleep state?
Any other side effects?
Thanks!
Device:
Hi parametrica,
Many thanks for your question online. Not sure what you are trying to accomplish, but SDK includes examples regarding timer 0 and timer 2. Please take a look at these examples. Both are located under projects\target_apps\peripheral_examples SDK path. Regarding the sleep mode, keep in mind that all peripheral domains including Timers are powered down. The system when operating in sleep mode is running with the Low Power Clock which can be either the internal RCX or the external XTAL32K oscillator. It will not prevent the chips enter the sleep mode. Also, it would be very helpful to share more inputs regarding your implementation.
In case of DA14531, Timer 1 can be kept active in sleep as the clock source is selectable between System Clock (sys_clk) and Low Power Clock (lp_clk). For getting more information, please refer to DA14531 Timer1 Software Example.
Thanks, PM_Dialog
Hi PM_Dialog,
Thank you for your support and sorry for my vague question. What I'm trying to conceive is the the rationale behind CLK_PER_REG[TMR_ENABLE] switch given that there are individual switches for both timers.
I have a program that uses both timers independently in different parts of the program. So I have to track the usage of both timers and switch CLK_PER_REG[TMR_ENABLE] on/off if any timer is used / none is used. My question is, do I really need to switch CLK_PER_REG[TMR_ENABLE] every time or can I just keep it always on for the sake of some code simplicity?
Thanks.
Hi parametrica,
Regarding Timer0, the 32 kHz clock is selected by default, so TIMER0_CTRL_REG [TIM0_CLK_SEL] bitfield is set to 0. The other four options can be selected by setting the TIM0_CLK_SEL bit and the TMR_ENABLE bitfields in the CLK_PER_REG . You can also control the frequency by the TMR_DIV bitfields. An additional clock divider is available that can be activated via bit TIM0_CLK_DIV of the timer control register TIMER0_CTRL_REG. Regarding, Timer 2 is clocked with the system clock divided by TMR_DIV (1, 2, 4 or 8) and can be enabled with TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]. You don’t need to switch clock every time. Also, I would suggest you to use our drivers provided within the SDK.
Thanks, PM_Dialog