CNT/DLY/FSM module don't generate down overflow pulse

Hi Ivan,

could you please share design example witn FSM settings?

It can be caused by too long waiting time because max counter value is 16383. If you are counting up from e.g. 16300 it means 83 clk pulses. At the same time if you switch to count down, counter will count from 16300 to zero which means 16300 clk pulses. If in addition the clk source is predivided, waiting time can be seconds or minutes. Please see attached design. The DFF is for "catching" output pulse because it's too short to see it on LED.

Thanks.