yes, the design should work correct in full specified voltage range, while all the general chip restrictions keeping . E.g. input voltage to PGA should not exceed 1000mV (PGA gain=1). Please refer to the device datasheet for full specification.//www.wsdof.com/sites/default/files/slg46620r111_09...
Thanks for the reply. Also, comment on the following: So for 5V input voltage can I set G=0.25 to get correct results i.e. a constant output indication at pin 15? Since the reference voltage of ADC can be set at 1.2V and input of PGA goes like 1.98/G according to the datasheet.
Hichughtaiah,
yes, the design should work correct in full specified voltage range, while all the general chip restrictions keeping . E.g. input voltage to PGA should not exceed 1000mV (PGA gain=1). Please refer to the device datasheet for full specification.//www.wsdof.com/sites/default/files/slg46620r111_09...
Thanks for your question!
Thanks for the reply. Also, comment on the following:
So for 5V input voltage can I set G=0.25 to get correct results i.e. a constant output indication at pin 15? Since the reference voltage of ADC can be set at 1.2V and input of PGA goes like 1.98/G according to the datasheet.
For 5V input voltage the better case is to set ADC reference VDD*0.25 option instead 1.2V and remind that input voltage shouldn't exceed VDD