Hi Dialog,
we developed a custom board for the DA14680 and experience a BOD reset every 8 seconds.
The BOR only occurs with DCDC on.
After a BOR event the CRG_TOP->BOD_STATUS_REG Register reads the Decimal value 19, sometimes 21. It indicates a problem with the 1V8 or 1V8P rail, but I can not find the cause.
The DA14680 is in a aQFN-60 package.
Additionally we use a slightly modified version of the ble_peripheral example and the lates SDK (SDK_1.0.14.1081)
Please find attached a trace of the BOR event.
The HIGH-Signal of the GPIO output is as follows:
1. Peak: The GPIO Port is set HIGH (port configured as input + pull-up) on entering the main() function and set immediately afterward to LOW (port configured as input + pull-down).
2. Peak: The GPIO Port is set HIGH (port configured as input + pull-up) on entering the vLPTimerCallback() function. It is set to LOW as part of the BOR I guess, because i did not set it to low manually.
3. Peak: The main() function got called again after the BOR event.
As stated in other forum posts and in the hardware guide a proper connection of the DCDC ground pad is important and a bad ground connection could be the cause. On the other hand you can see at the bottom side of the QFN package that all ground pads are interconnected.
Also the same code runs without issue on the DA14681 Development Kit - Basic.
Could you please give me additional help?
Hi martinfehre,
The most possible reason for the BOD issue is because of bad grounding. After 8 sec, the chip goes to sleep the first time, and will then start to use the DCDC. So, POR is caused when grounding is bad (BOD ref is lifted). Be aware that the 680 qfn60 package needs solid ground of ground pad. It is strongly recommended to apply about 9 vias in ground pad to ground layer and one via close to the DCDC buck ground pin. This pin is the ground between VBAT1, VBUS, VBAT2.
Thanks, PM_Dialog
Hi PM_Dialog,
please have a look at the pdf attached. It is a section of our top layer gerber file.
There are 16 vias in the ground pad with one near the DCDC ground stub. Do you have any recommendations?
Can you confirm that the GND pads are connected together on the chip?
Hi martinfehre,
According to the layout, the 680 seems to be well soldered to the center pad. The 16 vias to ground should be enough. We have dedicated ground pad for the blocks to reduce the noise, so not all ground pads should be connected on chip. It is strongly recommended to provide a solid ground on your PCB.
Thanks, PM_Dialog
Hi PM_Dialog,
I’m still searching for the BOR issue and the support in this forum has not been helpful thus far. You are basically repeating what’s written in the hardware design guide.
To double check if it is a layout problem of my PCB, a colleague of mine designed a second PCB - the results are the same.
We also experimented with different stencil thicknesses and pad cutouts to make sure the GND pads are properly connected. The soldering process is noticeably better, but it did not solve the BOR problem.
Eventually I began to doubt that the BOR is due to poor grounding. So I dived in the source code. After hours of reading the data sheet, debugging and testing I found this code in hw_cpm_dcdc_config(void):
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
DCDC->DCDC_V14_0_REG &= ~(REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_CUR_LIM_MIN) |
REG_MSK (DCDC,以便决定C_V14_0_REG, DCDC_V14_FAST_RAMPING));
DCDC->DCDC_V18_0_REG &= ~(REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_CUR_LIM_MIN) |
REG_MSK (DCDC,以便决定C_V18_0_REG, DCDC_V18_FAST_RAMPING));
DCDC->DCDC_V18P_0_REG &= ~(REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_CUR_LIM_MIN) |
REG_MSK (DCDC,以便决定C_V18P_0_REG, DCDC_V18P_FAST_RAMPING));
DCDC->DCDC_VDD_0_REG &= ~(REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_CUR_LIM_MIN) |
REG_MSK (DCDC,以便决定C_VDD_0_REG, DCDC_VDD_FAST_RAMPING));
#else
DCDC->DCDC_V14_0_REG &= ~REG_MSK(DCDC, DCDC_V14_0_REG, DCDC_V14_FAST_RAMPING);
DCDC->DCDC_V18_0_REG &= ~REG_MSK(DCDC, DCDC_V18_0_REG, DCDC_V18_FAST_RAMPING);
DCDC->DCDC_V18P_0_REG &= ~REG_MSK(DCDC, DCDC_V18P_0_REG, DCDC_V18P_FAST_RAMPING);
DCDC->DCDC_VDD_0_REG &= ~REG_MSK(DCDC, DCDC_VDD_0_REG, DCDC_VDD_FAST_RAMPING);
reg = DCDC->DCDC_CTRL_2_REG;
REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_LSSUP_TRIM, reg, 0);
REG_SET_FIELD (DCDC DCDC_CTRL_2_REG DCDC_HSGND_TRIM, reg, 0);
DCDC->DCDC_CTRL_2_REG = reg;
#endif
If I compiled the code written in #else and flashed the firmware to the DA14680, the BOR no longer occurred.
So I looked closer and narrowed the whole thing to 4 lines:
reg = DCDC->DCDC_CTRL_2_REG;
REG_SET_FIELD(DCDC, DCDC_CTRL_2_REG, DCDC_LSSUP_TRIM, reg, 0);
REG_SET_FIELD (DCDC DCDC_CTRL_2_REG DCDC_HSGND_TRIM, reg, 0);
DCDC->DCDC_CTRL_2_REG = reg;
These 4 lines prevent the microcontroller from restarting. What are these registry settings supposed do?
Hi martinfehre,
The code that you have posted is not related with the BOD issue. As I have already mentioned in my previous post reason for the BOD issue is because of bad grounding, so it is an issue on your custom PCB. Did you try to improve the bad grounding on your PCB?
Thanks, PM_Dialog
I too have exactly the same problem.
We have now made two boards and are still getting BOR after 8 seconds.
Hi point85,
Could you please check the grounding of your custom board? As I mentioned in a previous post, the most possible reason for the BOD issue is because of bad grounding.
Thanks, PM_Dialog
Yes I see that after the first board, so we made a second. Still receiving the same problem.
I have just discovered the 470nH inductor used does not meet the specification. Would this be likely to cause the same problem?
Hi point85,
we got rid of the BOR after switching to a 4 layer design. The ground layer is now 0.15 mm under the top layer. Before it was 1.5mm.
Thanks Martinfehre. Not quite sure what difference that would make on the design though.
Thanks Martinfehre. Not quite sure what difference that would make on the design though.
I have tried the new inductor on both boards and still have the same problem. Really stuck with this one.
Hi point85,
the answer is given by martinfehre. The 4 layer board fixed my BOR problem.