Question about Timer0 ON counter and instruction cycles

Hi ！
I designed a test about DA14580's Timer0 ON counter , in order to verify Timer0's working mechanism.

The initiation of timer 0 is :

#define PWM_HIGH 7

set_tmr_enable(CLK_PER_REG_TMR_ENABLED);
set_tmr_div(CLK_PER_REG_TMR_DIV_1);
timer0_init(TIM0_CLK_FAST, PWM_MODE_ONE, TIM0_CLK_NO_DIV);

time0on = ((PWM_HIGH+1) * 2)*1 -1; // make timer0 on counter = high + low
timer0_set(time0on, PWM_HIGH, PWM_HIGH);

timer0_start();

I got an 1Mhz PWM0 and PWM1 and an 1Mhz ON counter interrupt request.

The On counter test is :

register uint16 i,j,k;
i = *( volatile uint16*)(TIMER0_ON_REG);
j = *( volatile uint16*)(TIMER0_ON_REG);
k = *( volatile uint16*)(TIMER0_ON_REG);

The i,j,k output via UART after they got the TIMER0_ON_REG value.
Then I got the results :
i= 0003
j= 0000
k=000D

Keil gives ASM code of above code segment :

155: i = *( volatile uint16*)(TIMER0_ON_REG);
0x20000BCC 4826 LDR r0,[pc,#152] ; @0x20000C68
0x20000BCE 8845 LDRH r5,[r0,#0x02]
156: j = *( volatile uint16*)(TIMER0_ON_REG);
0x20000BD0 8846 LDRH r6,[r0,#0x02]
157: k = *( volatile uint16*)(TIMER0_ON_REG);
158:
159:
0x20000BD2 8847 LDRH r7,[r0,#0x02]

It seems that CPU runs as below sequence：
1 .load Timer0 ON Counter Register's Address to R0
2. Load the Timer0 ON Counter value to R5 (i);
3. Load the Timer0 ON Counter value to R6 (j);
4. Load the Timer0 ON Counter value to R7 (k);

According to ARM Cortex-M0 instruction summary, LDRH costs 2 clock cycles.
My question is if R5(i) got ' 0003' , after 2 clock cycles R6(j) should get '0001' and the same reason ,R7(k) shout get '000F'.
Is there something wrong in test design or something misunderstood about Timer0?

I attached the whole project. Plz verify it. Thanks a lot!