Hello,
I am using the reference from the system reset IC, but I need a longer delay, for which I cascaded two blocks as shown in the attachment. If the pulse disappears I would like the reset pulse to keep coming at the required interval. In emulation mode, I notice that the time is a little more than 3s for example according to the setting shown in the attachment. The actual time between subsequent pulses is about 3.4s. I'm afraid this error will build up if I increase the time. Is that due to an error in the design? I haven't programmed the chip yet, this test is in emulation mode. Thanks!
Attachment:
Device:
Hello vmore,
The issue you are experiencing is luckily quite fixable! If you notice, on the Delay time (typical) there is a blue formula ((Counter data +1) + variable)/clock, where "variable" is between 0 and 1. Since CNT0/DLY0 only has a counter value of 5 in your design this can be quite noticeable (up to half a second).
If you are increasing the overall delay this error shouldn't compile. However, if you'd like to make this deviation much less significant than it currently is I would recommend redistributing some of the counter data from CNT6/DLY6 to CNT0/DLY0. For example, a CNT6/DLY6 value of 50 and a CNT0/DLY0 value of 22 would give the same overall delay but with much less error.
I hope this helps! Let me know if this change doesn't improve the emulation and I'll continue to help your design in any way I can.
啊，我看。谢谢你的意思quick response, I'll play around with this.
Hello!
I hope you can assist me some more here. I notice that the CNT5/DLY5 generates a pulse as soon as the emulation or test mode with ext Vdd turns on. I am not very sure why that is triggered, since the counters haven't really hit their limits to trigger the pulse. How can I Modify the design to make sure this does not happen? If I get rid of the rest of my circuitry and just have the one shot trigger, I see that it gets triggered when emulation begins, so looks like the rest of my circuit is not the one setting this one-shot pulse off.
编辑:脉冲似乎联合国usually high in magnitude, about 5v even when I select test mode with external Vdd. On the scope, it actually looks like there is one tiny pulse followed by a longer one. What explains this? Please see attached picture
Hello vmore,
There is a good chance that this pulse is not related to the counter at all but actually due to the emulation configuration. Depending upon the pin, the advanced development board may send signals to the GreenPAK to configure your design. This signals can be seen across an oscilloscope in the order of microseconds, which would look like the pulse you've shown when viewed at a much larger time division, such as 250ms.
一种方法来确认这是问题是编程芯片并在测试模式下从DEV板运行模拟。由于不需要使用编程的IC来仿真配置，因此不应显示该脉冲。
If the emulator isn't the cause of the pulse then a debounce filter after the one-shot would prevent this pulse. This can be done by using another delay circuit and setting a both edge delay at a value higher than the errant pulse and lower than the one-shot pulse.
Let me know if you require further assistance, I'm happy to help!
Hi Alex,
So I just observed that these pulses only show up on the Test Points (on pretty much every test point) once the emulation/test is initiated and not at the expansion connector, which itself seems weird to me. If I use the expansion connector to connect my outputs, the initial stray pulse is not visible.
Thanks!
Hi vmore,
That's a promising sign that the pulse you are seeing is indeed the emulation configuring the GreenPAK; emulation configurations come across almost every pin. If you decrease the time divisions of the 'scope you should be able to see that there are separate bits coming across each pin. This would be a quick way of confirming that this is simply an emulation pulse and not inherent to your design.