您好对话框支持团队，
This is an urgent issue and inquiry.
We are using Smartsnippets Studio V1.6.3 for Windows OS and Jlink to download an 18K size FW into DA14580 but failed, the log is showed as below, could you pls read the log for us?
[INFO OTP Image @18-03-20 17:37:35] Header records have been removed from
hex file A00008_v1.0.hex.
[信息OTP图像@ 18-03-20 17:37:35]阅读18936
文件a00008_v1.0.hex中的字节。
[INFO General @18-03-20 17:39:38]
TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
[INFO General @18
-03-20 17:39:38] TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
[INFO
一般@ 18-03-20 17:39:40] ID不匹配。预期0223，发现C63B
[INFO
一般@ 18-03-20 17:39:40] ID不匹配。预期0223，发现C63B
[INFO
一般@ 18-03-20 17:39:40] ID不匹配。预期0223，发现C63B
[INFO
General @18-03-20 17:39:41] ID mismatch. Expected 0223, found C63B
[INFO
General @18-03-20 17:39:41] ID mismatch. Expected 0223, found C63B
[INFO
General @18-03-20 17:39:41] ID mismatch. Expected 0223, found C63B
[INFO
General @18-03-20 17:39:43] ID mismatch. Expected 0223, found C63B
[INFO
General @18-03-20 17:39:43] ID mismatch. Expected 0223, found C63B
[INFO
General @18-03-20 17:39:43] ID mismatch. Expected 0223, found C63B
[ERROR
一般@ 18-03-20 17:39:43]无法读取内存地址0x50003200
function JLINKARM_ReadMemHW
[ERROR General @18-03-20 17:39:43] No known
打开JLink连接时发现芯片。终止Proccess ...
[INFO General
@18-03-20 17:39:43] Ongoing debug mode already disabled.
[错误OTP图像
@18-03-20 17:39:43] Failed downloading firmware file to the board.
We attach the download failure logs into below, there are 2 types, one is by test jig & Jilink, another is wire connecting to PCBA directly & Jlink; download tool is same: Smartsnippets Studio V1.6.3 for Windows OS,
请支持弄清楚日志的含义。TKS。
BTW，对于原理图设计的下载电路，您认为6.7V电源和VPP引脚之间需要一个FET吗？是否需要在VBAT + JLink连接器RST引脚之间添加一个逆变器到DA14580 RST引脚？VPP电路中没有FET在RST引脚上没有逆变器。你认为这是OTP下载失败的原因吗？TKS。
Hi lawrencewu,
Looks like the device can't even connect via the Jlink to the tool as far as i can tell from the log that you have attached (the info showed by the SS toolbox are prompted by the jlink not the Smart Snippets Toolbox), are you using the CLI of Smart Snippets or the GUI (i suppose the GUI)? What is the sequence of operations on the OTP that you perform, and on which operation the error occurs ? I mean in case you are using the GUI do you hit the "Connect" to the OTP image ? Does the initial fw downloads (the one that will accept the commands from the OTP) ? Are you able to download code to the board using the jlink either via Keil or using the JTAG booter (on Smart Snippets)?
Regarding the needs that you describe above its depends on how you have implemented the production line and how you control the VPP, if you intent to use the extra GPIO that would control the VPP that the tool provides then yes the extra transistor in order to enable the high voltage should be part of your setup, but that doesn't have to do with what you are experiencing, you should be able to burn code in the OTP even if you applied the VPP manually. Regarding the inverter between the VBAT and the RST, since you are using JTAG interface and not UART you wont need the reset line in order to download code, if that is your concern.
Thanks MT_dialog
Hello Dialog team, our customer add the invertor between Jlink connector and module RST pin, she found that for same setting, some modules OTP download become success, however, some others are still failed. I attach the OK and NG logs, could you pls help to confirm again? We believe that it is GUI mode as customer is doing by manual, she hit the connect to the OTP image and then burn it by Jlink connector.
This is the failure log
Hi lawrencewu,
From the log that you have provided of the problematic procedure, the promt of Smart Snippets which mentions that "Adddittional error info at JTAG address 0x81FEC", we had a similar case where the same error turned out to be instabilities on the programming voltage.
Thanks MT_dialog
Hi,
There are both OTP FW download OK and NG cases, but the voltage is same.
我找到了一个类似的情况，即最终解决方案是
SWD-JTAG connection recommendations for connecting pull down resistor on SWCLK and pull up resistor on SWDIO lines.
https://support.dialog-semiconductor.com/otp-programming-1
Do you think this is one of potential reasons? TKS.
Hi lawrencewu,
我没有看到SWCLK上的下拉或在Pro开发套件的SWDIO线上的上拉，但值得尝试。
Thanks MT_dialog