Hi there,
I'm trying to read the voltage from a resistor divider (NTC thermistor and a fixed R) and get always too low values. Now I suspect that the ADC input loads down the rather high impedance source. So what are actually the ADC loading characteristics: Is there a sampling capacitor that loads the input pin - how large? Can you give some recommendation for the maximum source impedance of the signal connected to the ADC input?
/ Eero Heikkinen
Keywords:
Device:
Hi There,
The GPADC has no input buffer stage. During sampling phase a capacitor of 0.2 pF is switched to the input line. The pre-charge of this capacitor is at midscale level so the input impedance is infinite. Iff you are you using the attentuator , the 3x attenuator presents about a 300K input impedance.
BR JE_Dialog.
Thanks, that clarified a lot. Have you got any specifications for the 3x attenuation accuracy? Didn't find it in the datasheet.
BR Eero
Hi JE_Dialog
I'm designing an AFE connected to ADC pin,So I need know the input impendance to match the front end filter configure.As the signal range is 0-3v, I set the GP_ADC_ATTN3X.
So,Can I consider the ADC input constructure as following diagram?
******Risistors*****************
Signal
|
R1=200K
|------------------------>ADC
R2=100K
|
GND
************Capacitance*************
------->ADC
|
C=0.2pf
|
GND
Is C the sample/hold capacitance?
Thanks for any advice.
Hi bemoon,
Yes, what you are describing above is the circuitry of the ADC with the attenuator including the sample and hold capacitor and yes the value is 0.2pF.
Thanks MT_dialog
Hi Eero Heikkinen
Please check this posthttp://support.dialog-semiconductor.com/adc-issues
Hope it helps.
Thanks Marios.
Hi Eero, please find below. The key spec is that its a 300K input impedacne (resistor network 200K/100K divider). I don't have the spec details on the absolute accuracy, but i would assume that they are trimmed for ratio but not absolute value as is hte case with most resistive dividers in SAR ADC's. (I will check). BR JE_Dialog
"The 3x input attenuator is realized with a resistor
divider network. When bit
GP_ADC_CTRL_REG2[GP_ADC_ATTN3X] is set to
' 1 ',输入阻抗of the selected ADC input
channel becomes 300 k (typical) instead of infinite. In
addition, the resistor divider network will require more
settling time in the sampling phase. The general guideline
with bit GP_ADC_ATTN3X = 1 is: select the input
channel, then wait 1 s (16 clock cycles) before starting
the conversion. Only the required sampling time is
affected by the attenuator, the conversion time remains
approximately one clock cycle of 16 MHz (62.5 ns)."
Just a quick update ...the ADC resistors aren't rtimmed but are well define, so better than 1% tolerance on the ration.
ensure to is apply the 1µsec delay before taking the sample, else the reading is too low.
BR JE_Dialog