Hello,
Will the J-Link Edu work with the DA14580?
What pins are required to be broken out to connect to the device?
The reason I ask is that don't have the currently have the approved funding to buy the DA14580 dev kit to do a proof of concept. I have a limited budget, in which the dev kit will not fit into the prototype design case, hence I need to run my own board spin to get the verification complete. The university has said they need a MVP (minimum-viable-product) before they will give access to the complete funding pool for the research device.
I have read the application and reference design notes and think I can get most of it done. I am slightly confused about the memory of the device. The OTP programming can only be programmed once (hence one-time-programming), and during development the code must be loaded from UART or etc? So when using the J-Link does this send the data straight via SPI and then this is loaded into SRAM? And therefore the chip will not run in the developer mode without a J-Link attached.
Alternatively can I use the J-link to program external flash (or eeprom) spi memory then the chip reads from this?
I am just a little confused about the programming and where the data memory is stored. Your help will in this is much appreciated
问候，
Lance
Hello Lance，我将开始回答你的问题：我需要研究J-Link EDU。
OTP is one time only , you are correct. The device can boot from OTP or any external interface (also called development mode) which can be UART/SPI/I2C or you can download code straight into SRAM from UART etc.. . Downloading over UART etc will just copy straight into SRAM in development mode , or if you boot from external interface, it will copy contents into SRAM from EEPROM or FLASH. If nothing is programmed into OTP, the device will boot from external interface automatically - although programming the OTP can be used to speed up boot time with seconardy bootloader. Other things stored in OTP header file such as XTAL calibration can also be stored in external memory also, effectively copied into SRAM when the device boots from external source. The device is incredibly flexible : OTP can be completely left blank and use external FLASH, OTP can be programmed with just header file and external FLASH, OTP can be part programmed with bootloader and profile to speed up boot from external memory, or you can just use OTP. We have customers using all these scenarios. The flexibility also adds complexity to grasp this, so your question is very valid.
Smart Snippets tool will enable you to download from UART/JTAG and also program any external FLASH or EEPROM. Item 6.8 in the supported features below indicates this is now available.
http://support.dialog-semiconductor.com/sdk306-supported-features
您使用的是哪个开发板？我们有一个新的低成本$ 99板称为基本，拥有所需的所有元素：JTAG接口和函数闪存。
Thanks & BR
JE_Dialog
Hi there JE_Dialog,
Firstly thank you for your response, as I had gathered there are a lot of options in programming this chip. From what I can gather I can use an external flash ship to store the program memory and then have this load into SRAM on boot.
的开发板you mentioned (BASIC) seems to have the on board flash and JTAG, so in theory copying this reference design into my own custom design would work?
我是否能够利用基本的开发板来编程外部板（通过在我自己的连接器中删除痕迹和接线），或者这不推荐？
J-Link Edu is functionally identical to the basic Segger J-Link programmer, so in theory it would work but I was interested to know if you had any experience with it?
It sounds like the easiest option for me to go forward is to buy the BASIC dev kit, copy that chip and flash design (exclude the JTAG interface)and then modifiy this board to become my DA14580 programmer. Can you confirm that this indeed would work?
我确实对天线设计和介电常数有更多的疑问;但是，我会在适当的论坛中询问这些。此外，我还有关于供应链的疑问，大学是否应该在批量上市。
Thanks and regards,
Lance Henderson
Hello Lance, yes, you shuold be able to take the BASIC kit and copy that , and i cannot think of a reason why it could not be adapted to provide external board program - we have in fact some customers using the BASIC board in production environment for these purposes. We have no experience on the J-Link Edu right now. We will soon have an antenna reference design available - should be on line in a few days, which has passed FCC and CE , so that will be available to cut and pate and has all documentation available when its released.
BR JE_Dialog.