SLG46538-A

Dual supply, 17-GPIO, 4 ACMPs, 8-State ASM, I2C, 17 LUTS (max.), 7 CNT/DLY (max.), 8 DFF/LATCH (max.) and other Macrocells

The SLG46538-A provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46538. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The additional power supply (VDD2) on the SLG46538 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macro-cells designers can implement mixed-signal functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions.

四个模拟比较器（ACMP）;

两个电压参考（VREF）;

19个组合功能宏小区：

• 三个可选择的DFF /闩锁或2位LUT;
• One Selectable Continuous DFF/Latch or 3-bit LUT;
• 四个可选择的DFF /闩锁或3位LUT;
• 一个可选管延迟或3位LUT;
• 一个可选择的可编程功能发生器或2位LUT;
• Five 8-bit delays/counters or 3-bit LUTs;
• 两个16位延迟/计数器或4位LUT;
• 两个带边缘探测器的DELIGLITCH过滤器;

国家机器：

• Eight States;
• Flexible input logic from state transitions;

串行通信：

• I2C协议符合;

管道延迟 - 16级/ 3输出（组合功能宏子的一部分）;

可编程延迟;

One Inverter;

两个振荡器（OSC）：

• Configurable 25 kHz/2 MHz;
• 25.MHz RC Oscillator;

晶体振荡器;

力量-On-Reset (POR);

Eight Byte RAM + OTP User Memory:

• RAM Memory space that is readable and writable via I2C;
• User defined initial values transferred from OTP.

逻辑和混合信号电路

高度通用的宏小胶质

读取保护（读锁）

1.8 V（±5％）至5 V（±10％）VDD

1.8 V（±5％）至5 V（±10％）VDD2（VDD2≤VDD）

工作温度范围：-40°C至85°C

RoHS兼容/无卤素

AEC-Q100 Grade 1

P.ersonal Computers and Servers

P.C Peripherals

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身体电子

SLG46538-AP.: TQFN-20 (3.5 x 3.5 x 0.75 mm, 0.5 mm pitch)

产品ID后缀表示包装样式。